As is known in the art, a double-diffused metal-oxide-semiconductor (DMOS) device is a type of field-effect transistor that is capable of controlling large voltages and currents at its source and drain terminals. The terminals of a DMOS device are typically formed by a substrate, a polysilicon layer, and a heavily doped island in the substrate, with dielectric layers being provided intermediate the substrate, polysilicon layer and island to electrically insulate these structures from each other. DMOS devices typically include thousands of identical "active" cells, each of which is formed by a well (e.g., a P-well) and an island (e.g., an N+ region within the P-well) beneath holes formed in the polysilicon layer and the dielectric layer between the polysilicon layer and the substrate. A metal layer over the device has projections that extend through each of the holes and contacts the N+ regions.
When a positive voltage is applied to the polysilicon layer (the gate terminal of the device), the surface of each P-well is inverted, creating a channel through which electrons can laterally flow from the N+ region (the source terminal of the device) to the substrate, and thereafter downward through the substrate to a drain terminal.
The ruggedness of a semiconductor device is generally defined as the ability of the device to resist failure when its breakdown voltage is exceeded. In order to increase the breakdown voltage and the ruggedness of DMOS devices, a continuous field limiting ring (FLR) may be formed near the perimeter of the device. Field limiting rings are generally composed of an implant of the same impurity type as the wells (e.g., a p-type implant) in the surface of the substrate, such that the implant forms an edge-termination structure that encircles the active cells. Because it is continuous, the field limiting ring serves to reduce the high electric fields that occur in the presence of sharp corners. As such, the field limiting ring enables the device to sustain high voltages when the device is in the off-state. To further increase the off-state voltage capability of the device, multiple field limiting rings can be employed to further alleviate electric field crowding in the edge termination area of the device.
While providing the above benefits, prior art field limiting rings and other related structures occupy a significant portion of the surface area of the device without contributing to forward current conduction when the device is in its on-state. Furthermore, conventional field limiting ring processes entail additional mask, implant and diffusion steps in order to introduce the continuous ring of impurity in the substrate. Accordingly, prior art processes for forming field limiting rings contribute additional costs and processing to the device.
The prior art has employed techniques for the purpose of integrating the field limiting ring masking and implant steps into the DMOS process. For example, the masking step used to form the p-type implant of the field limiting ring has been employed to define a P+ region in the N+ region of each active cell, so as to reduce the gain of the NPN transistor formed by each active cell. The assignee of the present invention has developed an alternative to forming P+ regions in the active cells for the purpose of reducing gain. The process involves a silicon etch which allows the source metallization to directly contact the P-well beneath the N+ region, such that the prior art mask, implant and diffusion steps necessary to form the P+ region are obviated. This process also eliminates the need for a mask to block the N+ implant from the centers of the cells. By eliminating these masking operations and their associated alignment tolerances, this process also allows for increased cell density. However, such a process does not provide for the formation of a field limiting ring around the active cells of the device of the type described in the prior art.
In view of the above, it would be desirable if a process were available by which a field limiting ring could be formed in a DMOS device which did not entail additional mask, implant and diffusion steps beyond those required to form the P-well and N+ regions of the device's active cells. Such a process would preferably result in a field limiting ring which optimizes use of the surface area of the device by contributing to the current conduction of the device in the on-state.